从广义Chiplet互连设计出发，重点研究BGA区域孔串扰分析方法和优化措施。 提出以单元阵列孔建模计算作为全芯片BGA区域孔串扰评估方式，进一步根据不同布线层互连分析需求构建了多层扇出的孔建模平台。单元阵列孔建模分析结果和多层扇出孔阵建模分析结果相互印证，说明以单元阵列作为串扰评估最小单元是准确的，多层扇出孔阵建模方式是高效可行的。采用多层扇出孔阵建模平台对2种BGA封装管脚对应的PCB孔串扰进行了对比分析。 结果显示，在封装管脚设计时，提高邻近信号孔间距与邻近信号孔地孔间距比例比增加地孔数量和管脚间距更能有效地抑制串扰。

Aiming at the interconnect design in the extended Chiplet area, the analysis methods and optimization measures of via crosstalk in BGA region are mainly studied. Firstly, modeling & calculating on unit array vias is proposed to evaluate the crosstalk of the whole BGA area vias. Then, a multi-layer fan-out modeling platform is constructed for analysis requirements of different wiring layers. Results from several unit array models and multi-layer fan-out model verify each other, indicating that taking the array unit as the minimum part to evaluate the crosstalk is accurate, and the multi-layer fan-out modeling method is efficient and feasible. PCB vias crosstalk corresponding to two different BGA pin assignment is analyzed by multi-layer fan-out modeling. Results show that increasing the ratio of spacing between neighboring signal vias to spacing between neighboring signal via and ground via is more effective than increasing the quantity of ground vias or the BGA pitch.

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